1. Field of the Invention
The present invention relates to a wiring board such as a tape carrier substrate used for a chip-on-film (COF) and a method for manufacturing the same, and also relates to a semiconductor device using such a wiring board and a method for manufacturing the same. More particularly, the present invention relates to an improved protrusion electrode formed on a conductive wiring of a wiring board.
2. Description of Related Art
As one type of package modules using a film base, a COF has been known. FIG. 11 is a partial cross-sectional view showing a conventional COF. This COF includes a semiconductor element 2 mounted on a flexible insulating tape carrier substrate 1, which is protected by an encapsulation resin 3. The COF mainly is used as a driver for driving a flat panel display.
The tape carrier substrate 1 includes an insulating film base 4 made of polyimide or the like on which a plurality of conductive wirings 5 made of copper or the like are aligned. These conductive wirings 5 are connected with electrode pads 6 on the semiconductor element 2 via protrusion electrodes 7. A metal plated coating 8 and a solder resist layer 9 made of an insulating resin are formed on the conductive wirings 5 if necessary.
The protrusion electrodes 7 are formed with respect to the conductive wirings 5 on the tape carrier substrate 1 or the electrode pads 6 on the semiconductor element 2. In a wiring board described in JP 2004-327936 A, a protrusion electrode 7 is formed by metal plating conducted with respect to a conductive wiring 5 on a film base 4 as shown in FIG. 12A and FIG. 12B. FIG. 12A is a plan view, and FIG. 12B is a cross-sectional view taken along with the line F-F of FIG. 12A. This protrusion electrode 7 traverses the conductive wiring 5 and extends over both sides of the conductive wiring 5, that is, is bonded to the top face and the both side faces of the conductive wiring 5. Therefore, the relationship of “width S1 of the protrusion electrode 7”>“wiring width S2 of the conductive wiring 5” is established. This configuration ensures the sufficient stability of the protrusion electrode 7 against a force applied in the horizontal direction. Furthermore, as shown in FIG. 12B, this protrusion electrode 7 is in a convex sectional shape with a center portion higher than both end portions. Thereby, even when the protrusion electrode 7 is misaligned with respect to the electrode pad 6 on the semiconductor element 2, the possibility of the connection with an inappropriate electrode pad 6 can be reduced.
FIG. 13A is a plan view of a semiconductor device described in JP 2004-327936 A. FIG. 13A is a rear side view of the tape carrier substrate 1, where the film base 4 is illustrated with dashed lines and the remaining elements are illustrated with solid lines for the sake of clarity. FIG. 13B is a cross-sectional view taken along the line G-G of FIG. 13A.
When mounting the semiconductor element 2 to the tape carrier substrate 1 with a plurality of conductive wirings 5 aligned thereon as described above, there is a problem of a break 5x occurring in a conductive wiring 5 because of a stress applied to the conductive wiring 5 close to a protrusion electrode 7 due to a load or ultrasonic waves applied thereto.
Such a break will be a very serious problem because there is a demand to narrow a width of the conductive wiring 5 along with the need to narrow the pitch of the electrode pads 6 of the semiconductor element 2 resulting from a trend toward an increasing number of outputs of a COF, and thus there is a tendency to degrade the strength of the conductive wiring 5.
Especially in the case of the arrangement of the conductive wirings 5 as shown in FIG. 14, there is an increasing tendency toward a break due to the stress concentration. FIG. 14 is a front side view of the tape carrier substrate 1, in which unlike FIG. 13A a region 2a where the semiconductor element is to be mounted is illustrated with dashed lines.
Among a plurality of conductive wirings 5a to 5d aligned on the film base 4, the conductive wirings 5a are arranged with other conductive wirings (5a or 5b) adjacent thereto on both sides. On the other hand, the conductive wirings 5b located at both ends in a longitudinal direction of the semiconductor element mounting region 2a, the conductive wirings 5c located on the short sides and the conductive wirings 5d located in isolation do not have other conductive wirings adjacent thereto on at least one of both sides.
Such conductive wirings 5b to 5d without other conductive wirings adjacent thereto on one of both sides have an increasing tendency toward a break due to the stress concentration as compared with the conductive wirings 5a having other conductive wirings adjacent thereto on both sides.